Latch Read/Write Timing Fix
Alan Hightower identified a race condition with the rev 3 during NetPi-IDE development: IDE read/write lines were de-asserted before the latch interface completed its operations. This only manifested with very fast IDE devices. The fix was verified with an HP 1650A logic analyzer.
Turbo Clock Switcher - Engineering Application
Clock profile switcher for timing-sensitive software and test harnesses, enabling controlled transitions between true legacy rates and turbo operation.
- Profiles
- 4.77MHz, 8MHz, 12MHz, board turbo
- Switching Logic
- Debounced hardware line with deterministic latch state
- Feedback
- Status LED map plus software verification hooks
- Compatibility
- AT clones, 386SX, selected 486DX boards
- Use Cases
- Cycle-sensitive DOS software and diagnostics harnesses
- Field Harness
- Front-panel and relay control compatible
XT-Emporium NT